The basic structure of a HEMT device includes a current carrying active layer consisting of an epitaxial layer of high purity semiconductor such as gallium arsenide (GaAs) on a semi-insulating substrate. On top of the active layer is a thin, fairly heavily doped N-type gate layer of a wider gap semiconductor such as aluminum gallium arsenide (AlGaAs). On top of the gate layer is a Schottky barrier. The Schottky barrier is typically formed by depositing a layer of metal such as platinum on the aluminum gallium arsenide gate layer. The thickness and doping of the gate layers are chosen such that at the desired operating bias all electrons have been depleted from the gate layer underneath the Schottky barrier. Hence, the accumulated electrons in the potential notch on the active-layer side of the heterojunction carry the entire source-to-drain current in the device. By modulating the bias applied to the Schottky barrier gate, the bias across the heterojunction is modulated, which in turn modulates the sheet concentration of the accumulated electrons and hence the source to drain current. This electron region is also called the two dimensional electron gas (2-DEG) layer. Because the electron conduction takes place in a very thin, two-dimensional sheet adjacent to the gate layer, the device is also sometimes referred to as a two-dimensional electron gas FET.
Fabrication of gallium arsenide devices is generally more difficult than fabrication of silicon type devices. Fabrication of gallium arsenide devices capable of operating at microwave frequency involves the formation of sub-micron and micron features, as well as much larger structures, on and in the surface of a single crystal gallium arsenide chip. A gallium arsenide device is typically formed by providing a gallium arsenide single crystal wafer as the substrate for fabrication. Using either ion implantation or epitaxial deposition, a continuous N-type layer of aluminum gallium arsenide is formed over the entire wafer surface. To provide isolation, the N-type active layer is mesa etched to remove it from all areas of the wafer except where the active devices will be formed. This is done using conventional contact photolithography to pattern a photoresist layer to protect those areas of the surface where the active area is to remain during wet chemical etching.
Then the source/drain ohmic contact metallization is formed. A gold germanium nickel layer is evaporated and defined by photoresist liftoff, (liftoff being a preferred technique used extensively to pattern metals on gallium arsenide). Liftoff is preferred over etching because the gallium arsenide surfaces are readily damaged by many of the chemicals commonly employed to etch metal patterns and liftoff produces steeper metal edges. After deposition and liftoff of the source/drain metal layer, alloying at 430.degree. C. for three minutes forms ohmic contacts to the gallium arsenide. The ohmic contact metal layer is also used to form alignment marks used by the electron beam exposure system to precisely locate the critical sub-micron gate pattern.
The gate region is formed by electron beam exposure and development of a photoresist mask layer, then the gate area is recessed using a wet etch to achieve the desired device current, and then a metal, usually titanium, platinum, gold or some other combination, is evaporated and defined by a liftoff process similar to that used for ohmic contacts. A major problem with the gate recessed etch step is that it is time-consuming, inaccurate and often subjects the thin, sensitive, molecular beam epitaxial layers to caustic etchants and exposes the underlying layers to air resulting in oxidation.
After the metal gate is deposited, it is alloyed to the gallium arsenide layer by heat. Thin, sequential layers of titanium and gold are deposited and patterned by liftoff to overlay the alloyed source and drain regions and to overlay the alloy gate region to reduce the spreading resistance. These layers of gold and titanium also reduce microwave loses in various components.
In some gallium arsenide devices the ohmic contacts are formed after the gate metallization step. When the ohmic contacts to the source and drain regions are alloyed, the heat used in the alloying step can cause further diffusion of the Schottky barrier metal material, such as platinum, into the gallium arsenide region. Gate metal diffusion into the substrate is a major problem in gallium arsenide device fabrication.
A. K. Sinha et al. in their article entitled, "n-GaAs Schottky Diodes Metallized with Ti and Pt/Ti", Solid-State Electronics, vol. 19, pp. 489-492, 1976, discuss the electrical characteristics and interdiffusion in n-GaAs Schottky diodes containing titanium and platinum titanium gate metallization. This paper also describes basic materials science and Schottky properties of the platinum gallium arsenide interface. N. Toyoda et al., "An Application of Pt--GaAs Solid Phase Reaction to GaAs and Related Compounds", in Gallium Arsenide and Related Compounds 1981, Institute of Physics Conference Serial 63, Bristol and London, Institute of Physics, p. 521 (1982), discuss the problems of the basic platinum gallium arsenide junction. Toyoda et al. note that the platinum gallium arsenide junction shows good Schottky characteristics after being sintered below 500.degree. C. while it degrades above 500.degree. C. At 400.degree. C. platinum reacts with gallium arsenide at the diffusion limited rate in the early stage, and completely reacts after a later period of time.